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HIP6500
Data Sheet December 1999 File Number 4774.1
Multiple Linear Power Controller with ACPI Control Interface
The HIP6500 complements either an HIP6020 or an HIP6021 in ACPI-compliant designs for microprocessor and computer applications. The IC integrates two linear controllers and two regulators, switching, monitoring and control functions into a 20-pin SOIC package. One linear controller generates the 3.3VDUAL voltage plane from the ATX supply's 5VSB output, powering the PCI slots through an external pass transistor during sleep states (S3, S4/S5). A second transistor is used to switch in the ATX 3.3V output for operation during S0 and S1/S2 (active) operating states. The second linear controller supplies the computer system's 2.5V/3.3V memory power through an external pass transistor in active states. During S3 state, an integrated pass transistor supplies the 2.5V/3.3V sleep power. A third controller powers up the 5VDUAL plane by switching in the ATX 5V output in active states, and the ATX 5VSB in sleep states. The two internal regulators consist of a low current 3.3V sleep output and a dedicated, noise-free 2.5V clock chip supply. The HIP6500's operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3 and S5. Further control of the logic governing activation of different power states is offered through two configuration pins, EN3VDL and EN5VDL. In active state, the 3.3VDUAL linear regulator uses an external N-Channel pass MOSFET to connect the output directly to the 3.3V input supplied by an ATX (or equivalent) power supply, for minimal losses. In sleep state, power delivery on the 3.3VDUAL output is transferred to an NPN transistor, also external to the controller. Active state power delivery for the 2.5/3.3VMEM output is performed through an external NPN transistor, or an NMOS switch for the 3.3V setting. In sleep state, conduction on this output is transferred to an internal pass transistor. The 5VDUAL output is powered through two external MOS transistors. In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output; while in active state, current flow is transferred to an NMOS transistor connected to the ATX 5V output. Similar to the 3.3VDUAL output, the operation of the 5VDUAL output is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well. The 3.3VSB internal regulator is active for as long as the ATX 5VSB voltage is applied to the chip, and derives its output current from the 5VSB pin. The 2.5VCLK output is only active during S0 and S1/S2, and uses the 3V3 pin as input source for its internal pass element.
Features
* Provides 5 ACPI-Controlled Voltages - 5V Active/Sleep (5VDUAL) - 3.3V Active/Sleep (3.3VDUAL) - 2.5V/3.3V Active/Sleep (2.5VMEM) - 3.3V Always Present (3.3VSB) - 2.5V Clock (Active Only) (2.5VCLK) * Excellent Output Voltage Regulation - 3.3VDUAL Output: 2.0% Over Temperature; Sleep State Only - 2.5V/3.3VMEM Output: 2.0% Over Temperature; Both Operational States (3.3V setting in sleep only) - 2.5VCLK and 3.3VSB Output: 2.0% Over Temperature * Small Size - Very Low External Component Count * Selectable Memory Output Voltage Via FAULT/MSEL Pin - 2.5V for RDRAM Memory - 3.3V for SDRAM Memory * Under-Voltage Monitoring of All Outputs with Centralized FAULT Reporting and Temperature Shutdown
Applications
* Motherboard Power Regulation for ACPI-Compliant Computers
Pinout
HIP6500 (SOIC) TOP VIEW
20 EN3VDL 19 DRV2 18 5V 17 12V 16 SS 15 5VDL 14 5VDLSB 13 DLA 12 FAULT/MSEL 11 GND
VSEN2
1
5VSB 2 3V3SB 3 3V3DLSB 4 3V3DL 5 VCLK 6 3V3 7 EN5VDL S3 8 9
S5 10
Ordering Information
PART NUMBER HIP6500CB HIP6500EVAL1 TEMP. RANGE (oC) 0 to 70 PACKAGE 20 Ld SOIC PKG. NO. M20.3
Evaluation Board
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
Block Diagram
12V 3V3DLSB 3V3DL 5V 3V3 5VSB 5VDLSB DLA
EA4 + 12V MONITOR 10.2V/9.2V + 3.75V 5VDL UV COMPARATOR
5VSB POR 4.5V/4.0V TEMPERATURE MONITOR (TMON)
TO 5VSB
EA3
+
3V3SB TO UV DETECTOR MONITOR AND CONTROL + TO UV DETECTOR EA3 TO 3V3
FAULT/MSEL
UV DETECTOR
TO 5VSB 40A + 10A TO UV DETECTOR EA2
-
GND
SS
2
S3 S5 EN3VDL EN5VDL
HIP6500
VCLK
+ 1.265V
TO 5V
DRV2
+
VSEN2
FIGURE 1.
HIP6500 Simplified Power System Diagram
+5VIN +12VIN +5VSB +3.3VIN 3.3VSB 3.3V Q2 3.3VDUAL 3.3V FAULT/MSEL Q3 LINEAR CONTROLLER LINEAR REGULATOR LINEAR CONTROLLER Q1 VMEM 2.5V/3.3V VCLK 2.5V Q5 5VDUAL 5V SHUTDOWN SX ENXVDL 2 2 Q4
LINEAR REGULATOR
HIP6500
CONTROL LOGIC
FIGURE 2.
Typical Application
+5VIN +12VIN +5VSB +3.3VIN
12V VOUT1 3.3VSB COUT1 5V 3V3DLSB 3V3SB
3V3
5VSB
DRV2 VSEN2
Q1
Q2 Q3 VOUT3 3.3VDUAL COUT3
VOUT2 2.5/3.3VMEM
COUT2 3V3DL FAULT/MSEL VCLK VOUT4
HIP6500
FAULT RSEL
2.5VCLK COUT4 Q4
5VDLSB SLP_S3 SLP_S5 EN5VDL EN3VDL S3 S5 EN5VDL EN3VDL SS CSS SHUTDOWN GND 5VDL COUT5 DLA Q5 VOUT5 5VDUAL
FIGURE 3.
3
HIP6500
Absolute Maximum Ratings
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V 12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Digital Inputs, VSX, VEN5VDL, VEN3VDL . . . . . . . . . . . . 0 to +5.25V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Nominal Supply Current Shutdown Supply Current
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
I5VSB I5VSB(OFF) VSS = 0.8V
-
30 14
-
mA mA
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS Rising 5VSB POR Threshold 5VSB POR Hysteresis Rising 12V Threshold 12V Hysteresis Rising 3V3 and 5V Thresholds 3V3 and 5V Hysteresis Soft-Start Current Shutdown Voltage Threshold 3.3VSB LINEAR REGULATOR (VOUT1) Regulation 3V3SB Nominal Voltage Level 3V3SB Undervoltage Rising Threshold 3V3SB Undervoltage Hysteresis 3V3SB Output Current 2.5/3.3VMEM LINEAR REGULATOR (VOUT2) Regulation VSEN2 Nominal Voltage Level VSEN2 Nominal Voltage Level VSEN2 Undervoltage Rising Threshold VSEN2 Undervoltage Hysteresis (Note 2) VSEN2 Output Current DRV2 Output Drive Current DRV2 Output Impedance IVSEN2 IDRV2 5VSB = 5V 5VSB = 5V, RSEL = 1k RSEL = 10k VVSEN2 VVSEN2 RSEL = 1k RSEL = 10k 250 220 2.5 3.3 83 3 300 200 2.0 % V V % % mA mA I3V3SB 5VSB = 5V V3V3SB 250 3.3 2.77 110 300 2.0 % V V mV mA ISS VSD 0.2 1.0 90 5 10 4.5 10.2 0.8 V V V V % % A V
4
HIP6500
Electrical Specifications
PARAMETER 3.3VDUAL LINEAR REGULATOR (VOUT3) Sleep State Regulation 3V3DL Nominal Voltage Level 3V3DL Undervoltage Rising Threshold 3V3DL Undervoltage Hysteresis 3V3DLSB Output Drive Current DLA Output Impedance 2.5VCLK LINEAR REGULATOR (VOUT4) Regulation VCLK Nominal Voltage Level VCLK Undervoltage Rising Threshold VCLK Undervoltage Hysteresis VCLK Output Current (Note 3) 5VDUAL SWITCH CONTROLLER (VOUT5) 5VDL Undervoltage Rising Threshold 5VDL Undervoltage Hysteresis 5VDLSB Output Drive Current 5VDLSB Pull-up Impedance to 5VSB TIMING INTERVALS Active State Assessment Past Input UV Thresholds (Note 4) Active-to-Sleep Control Input Delay CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT/MSEL) High Level Input Threshold Low Level Input Threshold S3, S5 Internal Pull-Up Impedance to 5VSB FAULT Output Impedance TEMPERATURE MONITOR Fault-Level Threshold (Note 5) Shutdown-Level Threshold (Note 5) NOTES: 2. Valid for 3.3V setting only. 3. At ambient temperatures less than 50oC. 4. Guaranteed by correlation. 5. Guaranteed by design. 140 155 oC oC
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
V3V3DL I3V3DLSB 5VSB = 5V 5 -
3.3 2.77 110 8.5 90
2.0 -
% V V mV mA
VVCLK IVCLK V3V3 = 3.3V 500
2.5 2.10 80 800
2.0 -
% V V mV mA
I5VDLSB 5VDLSB = 4V, 5VSB = 5V -20 -
4.22 170 350
-40 -
V mV mA
20 -
25 200
30 -
ms s
0.8 FAULT = high -
70 100
2.2 -
V V k
5
HIP6500 Functional Pin Description
3V3 (Pin 7)
Connect this pin to the ATX 3.3V output. This pin provides the output current for the 2V5CLK pin, and is monitored for power quality.
SS (Pin 16)
Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1F recommended). The internal soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ramp-up of the output voltages. Pulling this pin low with an open-drain device shuts down all the outputs as well as forces the FAULT pin low. The CSS capacitor is also used to provide a controlled voltage slew rate during active-tosleep transitions on the 3.3VDUAL, and VMEM outputs.
5VSB (Pin 2)
Provide a very well de-coupled 5V bias supply for the IC to this pin by connecting it to the ATX 5VSB output. This pin provides the output current for the 3V3SB and VSEN2 pins, as well as the base current for Q2. The voltage at this pin is monitored for power-on reset (POR) purposes.
VSEN2 (Pin 1)
Connect this pin to the memory output (VOUT2). In sleep states, this pin is regulated to 2.5V or 3.3V (based on RSEL) through an internal pass transistor capable of delivering 300mA (typically). When VOUT2 is programmed to 2.5V, the active-state voltage at this pin is regulated through an external NPN transistor connected at the DRV2 pin. For the 3.3V setting, the ATX 3.3V is passed to this pin through a fully on external N-MOS transistor. During all operating states, the voltage at this pin is monitored for under-voltage events.
5V (Pin 18)
Connect this pin to the ATX 5V output. This pin provides the base bias current for Q1, and is monitored for power quality.
12V (Pin 17)
Connect this pin to the ATX 12V output. This pin provides the gate bias voltage for Q3 and Q5, and is monitored for power quality.
DRV2 (Pin 19)
For the 2.5V RDRAM systems connect this pin to the base of a suitable NPN transistor. This pass transistor regulates the 2.5V output from the ATX 3.3V during active states operation. For 3.3V SDRAM systems connect this pin to the gate of a suitable N-MOS transistor; this transistor is used to switch in the ATX 3.3V output.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured with respect to this pin.
S3 and S5 (Pins 9 and 10)
These pins switch the IC's operating state from active (S0, S1/S2) to S3 and S4/S5 sleep states. These are digital inputs featuring internal 50k (typical) resistor pull-ups to 5VSB. Internal circuitry de-glitches these pins for disturbances lasting as long as 2s (typically). Additional circuitry blocks any illegal state transitions (such as S3 to S4/S5 or vice versa). Respectively, connect S3 and S5 to the computer system's SLP_S3 and SLP_S5 signals.
3V3DL (Pin 5)
Connect this pin to the 3.3V dual output (VOUT3). In sleep states, the voltage at this pin is regulated to 3.3V; in active states, ATX 3.3V output is delivered to this node through a fully on N-MOS transistor. During all operating states, this pin is monitored for under-voltage events.
EN3VDL and EN5VDL (Pins 20 and 8)
These pins control the logic governing the dual outputs' behavior in response to S3 and S4/S5 requests. These are digital inputs whose status can only be changed during active states operation or during chip shutdown (SS pin grounded by external open-drain device or chip bias below POR level). The input information is latched-in when entering a sleep state, as well as following 5VSB POR release or exit from shutdown. EN3VDL features an internal 50k pull-down resistor, while EN5VDL is internally pulled high through a similar resistor.
3V3DLSB (Pin 4)
Connect this pin to the base of a suitable NPN transistor. In sleep state, this transistor is used to regulate the voltage at the 3V3DL pin to 3.3V.
DLA (Pin 13)
Connect this pin to the gates of suitable N-MOSFETs, which in active state, switch in the ATX 3.3V and 5V outputs into the 3.3VDUAL and 5VDUAL outputs, respectively.
5VDL (Pin 15)
Connect this pin to the 5VDUAL output (VOUT5). In either operating state, the voltage at this pin is provided through a fully on MOS transistor. This pin is also monitored for undervoltage events.
FAULT/MSEL (Pin 12)
This is a multiplexed function pin allowing the setting of the memory output voltage to either 2.5V or 3.3V (for RDRAM or SDRAM memory systems). In case of an undervoltage on any of the outputs or on any of the monitored ATX outputs, or in case of an overtemperature event, this pin is used to report the fault condition by being pulled to 5VSB.
5VDLSB (Pin 14)
Connect this pin to the gate of a suitable P-MOSFET or bipolar PNP. In sleep state, this transistor is switched on, connecting the ATX 5VSB output to the 5VDUAL regulator output.
6
HIP6500
3V3SB (Pin 3)
This pin is the output of the internal 3.3VSB regulator (VOUT1). This internal regulator operates continuously for as long as the 5VSB bias voltage is applied to the HIP6500. This pin is monitored for under-voltage events. As seen in Table 1, EN3VDL simply controls whether the 3.3VDUAL plane remains powered up during S4/S5 sleep state.
TABLE 2. 5VDUAL OUTPUT (VOUT5) TRUTH TABLE EN5VDL S5 1 1 0 0 1 1 0 0 S3 1 0 1 0 1 0 1 0 5VDL 5V 0V Note 0V 5V 5V Note 5V COMMENTS S0, S1 States (Active) S3 Maintains Previous State S4/S5 S0, S1 States (Active) S3 Maintains Previous State S4/S5
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator (VOUT4). This internal regulator operates only in active states (S0, S1/S2) and is shut off during any sleep state, regardless of the configuration of the chip. This pin is monitored for under-voltage events.
0 0 0 0 1 1 1 1
Description
Operation
The HIP6500 controls 5 output voltages (Refer to Figures 1, 2, and 3). It is designed for microprocessor computer applications with 3.3V, 5V, 5VSB, and 12V bias input from an ATX power supply. The IC is composed of two linear controllers supplying the PCI slots' 3.3VAUX power (VOUT3) and the 2.5V RDRAM or 3.3V SDRAM memory power (VOUT2), two linear regulators providing an always-present 3.3VSB (VOUT1), and a dedicated 2.5V clock chip supply (VOUT4), a dual switch controller supplying the 5VDUAL voltage (VOUT5), as well as all the control and monitoring functions necessary for complete ACPI implementation.
NOTE: Combination Not Allowed.
Similarly, Table 2 details the fact that EN5VDL status controls whether the 5VDUAL plane supports the S3-S5 sleep states.
TABLE 3. 2.5/3.3VMEM OUTPUT (VOUT2) TRUTH TABLE RSEL 1k 1k S5 1 1 0 0 1 1 0 0 S3 1 0 1 0 1 0 1 0 2.5/3.3VMEM 2.5V 2.5V Note 0V 3.3V 3.3V Note 0V COMMENTS S0, S1 States (Active) S3 Maintains Previous State S5 S0, S1 States (Active) S3 Maintains Previous State S5
Initialization
The HIP6500 automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the 5VSB input supply voltage, initiating 3.3VSB soft-start operation after exceeding POR threshold. At 3ms (typically) after 3.3VSB finishes its ramp-up, the ENxVDL status and the memory voltage (VMEM) setting are latched in and the chip proceeds to ramp up the remainder of the voltages, as required.
1k 1k 10k 10k 10k 10k
NOTE: Combination Not Allowed.
Operational Truth Tables
The EN3VDL and EN5VDL pins offer a choice of 4 configurations in terms of the overall system architecture and supported features. Tables 1-3 describe the truth combinations pertaining to each of the three outputs.
TABLE 1. 3.3VDUAL OUTPUT (VOUT3) TRUTH TABLE EN3VDL 0 0 0 0 1 1 1 1 S5 1 1 0 0 1 1 0 0 S3 1 0 1 0 1 0 1 0 3V3DL 3.3V 3.3V Note 3.3V 3.3V 3.3V Note 0V COMMENTS S0, S1 States (Active) S3 Maintains Previous State S4/S5 S0, S1 States (Active) S3 Maintains Previous State S4/S5
As seen in Table 3, 2.5/3.3VMEM output is maintained in S3 (suspend to RAM) sleep state only. The dual-voltage support accommodates both SDRAM as well as RDRAM type memories. Not shown in any of the tables are the 3.3VSB and the 2.5VCLK outputs. The 3.3VSB output powers up as soon as the 5VSB ATX output is available. The 2.5VCLK output operation is restricted by the chip's POR and is only available in active state (S0, S1). For additional information, see the soft-start sequence diagrams. Additionally, the internal circuitry does not allow the transition from an S3 (suspend to RAM) state to an S4/S5 (suspend to disk/soft off) state or vice versa. The only `legal' transitions are from an active state (S0, S1) to a sleep state (S3, S5) and vice versa.
NOTE: Combination Not Allowed.
7
HIP6500
Functional Timing Diagrams
Figures 4 through 8 are timing diagrams, detailing the power up/down sequences of all three outputs in response to the status of the enable (EN3VDL, EN5VDL) and sleep-state pins (S3, S5), as well as the status of the ATX supply. The status of the EN3VDL and EN5VDL pins can only be changed while in active (S0, S1) states, when the bias supply (5VSB pin) is below POR level, or during chip shutdown (SS pin shorted to GND); a status change of these two pins while in a sleep state is ignored. Not shown in these diagrams is the deglitching feature used to protect against false sleep state tripping. Both S3 and S5 pins are protected against noise by a 2s filter (typically 1 4s). This feature is useful in noisy computer environments if the control signals have to travel over significant distances. Additionally, the S3 pin features a 200s delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200s interval, if the S5 pin is low, the HIP6500 switches into S5 sleep state; if the S5 pin is high, the HIP6500 goes into S3 sleep state.
5VSB S3 S5 12V 3V3DLSB DLA 3V3DL 5VDLSB 5VDL
5VSB S3 S5 12V 3V3DLSB DLA 3V3DL 5VDLSB 5VDL
FIGURE 4. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR EN3VDL = 1, EN5VDL = 1
FIGURE 6. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR EN3VDL = 0, EN5VDL = 1
5VSB S3 S5 12V 3V3DLSB DLA 3V3DL 5VDLSB 5VDL
5VSB S3 S5 12V 3V3DLSB DLA 3V3DL 5VDLSB 5VDL
FIGURE 5. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR EN3VDL = 1, EN5VDL = 0
FIGURE 7. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR EN3VDL = 0, EN5VDL = 0
8
HIP6500
Figure 9 shows the soft-start sequence for the typical application start-up in sleep state with all output voltages enabled. At time T0 5VSB (bias) is applied to the circuit. At time T1 the 5VSB surpasses POR level. An internal fast charge circuit quickly raises the SS capacitor voltage to approximately 1V, then the 10A current source continues the charging. The soft-start capacitor voltage reaches approximately 1.25V at time T2, at which point the 3.3VSB error amplifiers' reference input starts its transition, causing the output voltage to ramp up proportionally. The ramp-up continues until time T3 when the 3.3VSB voltage reaches the set value. After the 3.3VSB reached its set value, as the softstart capacitor voltage reaches approximately 2.75V, the under-voltage monitoring circuit of this output is activated and the soft-start capacitor is quickly discharged to approximately 1.25V. Following the 3ms (typical) time-out between T3 and T4, the memory and enabling pins' selection are latched in, and the soft-start capacitor commences a second ramp-up designed to smoothly bring up the remainder of the voltages required by the system. At time T5 all voltages are within regulation limits, and as the SS voltage reaches 2.75V, all the UV monitors are activated and the SS capacitor is quickly discharged to 1.25V, where it remains until the next transition.
+12VIN INPUT VOLTAGES (2V/DIV) +5VSB 5VSB (1V/DIV) SOFT-START (1V/DIV) 0V OUTPUT VOLTAGES (1V/DIV) VOUT1 (3.3VSB) VOUT5 (5VDUAL) VOUT3 (3.3VDUAL) VOUT2, 4 (2.5VMEM, 2.5VCLK) +5VIN +3.3VIN SOFT-START (1V/DIV) DLA PIN (2V/DIV)
5VSB S3 S5 12V INTERNAL VSEN2 DEVICE DRV2 VSEN2 3V3SB VCLK
FIGURE 8. 2.5/3.3VMEM, 3.3VSB AND VCLK TIMING DIAGRAM
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5) The 5VSB POR function initiates the soft-start sequence. An internal 10A current source charges an external capacitor. The error amplifiers reference inputs are clamped to a level proportional to the SS (soft-start) pin voltage. As the SS pin voltage slews from about 1.25V to 2.5V, the input clamp allows a rapid and controlled output voltage rise.
VOUT5 (5VDUAL)
0V
VOUT1 (3.3VSB) OUTPUT VOLTAGES (1V/DIV)
VOUT3 (3.3VDUAL)
VOUT2 (2.5VMEM)
0V VOUT4 (2.5VCLK)
T0
T1
0V
T2 TIME
T3
T0 T1 T2
T3
T4 TIME
T5
FIGURE 10. SOFT-START INTERVAL IN ACTIVE STATE (2.5/3.3VMEM OUTPUT SHOWN IN 2.5V SETTING)
FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE (ALL OUTPUTS ENABLED)
9
HIP6500
SOFT-START INTO ACTIVE STATES (S0, S1) If both S3 and S5 are logic high at the time the 5VSB is applied, the HIP6500 will assume active state wake-up and keep off the controlled external transistors and the VCLK output until some time (typically 25ms) after the ATX's main outputs used by the application (3.3V, 5V, and 12V) exceed the set thresholds. This time-out feature is necessary in order to insure the main ATX outputs are stabilized. The time-out also assures smooth transitions from sleep into active when sleep states are being supported. 3.3VSB output, whose operation is only dependent on 5VSB presence, will come up right as bias voltage reaches POR level. During sleep to active state transitions from conditions where the outputs are initially 0V (such as S5 to S0 transition with EN3VDL = 1 and EN5VDL = 0, or simple power-up sequence directly into active state), the 3VDUAL and 5VDUAL outputs go through a quasi soft-start by being pulled high through the body diodes of the N-Channel MOSFETs connected between these outputs and the 3.3V and 5V ATX outputs. Figure 10 shows this start-up. 5VSB is already present when the main ATX outputs are turned on at time T0. As a result of +3.3VIN and +5VIN ramping up, the 3.3VDUAL and 5VDUAL output capacitors charge up through the body diodes of Q3 and Q5, respectively (see Figure 3). At time T1, all main ATX outputs exceed the HIP6500's undervoltage thresholds, and the internal 25ms (typical) timer is initiated. At T2 the time-out initiates a soft-start, and the memory and clock outputs are ramped-up, reaching regulation limits at time T3. Simultaneous with the beginning of the memory and clock voltage ramp-up, at time T2, the DLA pin is pulled high, turning on Q3 and Q5 in the process, and bringing the 3.3VDUAL and 5VDUAL outputs in regulation. Shortly after time T3, as the SS voltage reaches 2.75V, the soft-start capacitor is quickly discharged down to approximately 2.45V, where it remains until a valid sleep state request is received from the system. controlled through an internal pass transistor, will set off the FAULT flag, and it will shut off the faulting regulator only. If shutdown or latch off of the entire circuit is desired in case of a fault, regardless of the cause, this can be achieved by externally pulling or latching the SS pin low. Pulling the SS pin low will also force the FAULT pin to go low and reset an internally latched-off output. Special consideration is given to the initial start-up sequence. If, following a 5VSB POR event, the 3.3VSB output is ramped up and is subject to an undervoltage event before the remainder of the controlled voltages have been brought up, then the FAULT output goes high and the entire IC latches off. Latch-off condition can be reset by cycling the bias power (5VSB). Undervoltage events on the 3.3VSB output at any other times are handled according to the description found in the second paragraph under the current heading. Another condition that could set off the FAULT flag is chip over-temperature. If the HIP6500 reaches an internal temperature of 140oC (typical), the FAULT flag is set off, but the chip continues to operate until the temperature reaches 155oC (typical), when unconditional shutdown of all outputs takes place. Operation resumes at 140oC and the temperature cycling occurs until the fault-causing condition is removed.
Output Voltages
The output voltages are internally set and do not require any external components. Selection of the VMEM memory voltage is done by means of an external resistor connected between the FAULT/MSEL pin and ground. An internal 40A (typical) current source creates a voltage drop across this resistor. Following every 3.3VSB ramp-up or chip reset (see Soft-Start Circuit), this voltage is compared with an internal reference and the setting is latched in. Based on this comparison, the output voltage is set at either 2.5V (RSEL = 1k), or 3.3V (RSEL = 10k). It is very important that no capacitor is connected to the FAULT/MSEL pin; the presence of a capacitive element at this pin can lead to false memory voltage selection. See Figure 11 for details.
Fault Protection
All the outputs are monitored against undervoltage events. A severe overcurrent caused by a failed load on any of the outputs, would, in turn, cause that specific output to suddenly drop. If any of the output voltages drop below 80% (typical) of their set value, such event is reported by having the FAULT/MSEL pin pulled to 5V. Additionally, exceeding the maximum current rating of an integrated regulator (output with pass regulator on chip) can lead to output voltage drooping; if excessive, this droop can ultimately trip the under-voltage detector and send a FAULT signal to the computer system. A FAULT condition occurring on an output when controlled through an external pass transistor will only set off the FAULT flag, and it will not shut off or latch off any part of the circuit. A FAULT condition occurring on an output when
RSEL 1k 10k
VMEM 2.5V 3.3V 40A
5VSB
FAULT/MSEL
MEM VOLTAGE SELECT COMP +
RSEL +
-
0.2V
FIGURE 11. 2.5/3.3VMEM OUTPUT VOLTAGE SELECTION CIRCUITRY DETAILS
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HIP6500 Application Guidelines
Soft-Start Interval
The 5VSB output of a typical ATX supply is capable of 725mA. During power-up in a sleep state, it needs to provide sufficient current to charge up all the output capacitors and simultaneously provide some amount of current to the output loads. Drawing excessive amounts of current from the 5VSB output of the ATX can lead to voltage collapse and induce a pattern of consecutive restarts with unknown effects on the system's behavior or health. The built-in soft-start circuitry allows tight control of the slewup speed of the output voltages controlled by the HIP6500, thus enabling power-ups free of supply drop-off events. Since the outputs are ramped up in a linear fashion, the current dedicated to charging the output capacitors can be calculated with the following formula:
I SS I COUT = ----------------------------- x ( C OUT x V OUT ) , where C SS x V BG
Layout Considerations
The typical application employing a HIP6500 is a fairly straight forward implementation. Like with any other linear regulator, attention has to be paid to the few potentially sensitive small signal components, such as those connected to sensitive nodes or those supplying critical by-pass current. The power components (pass transistors) and the controller IC should be placed first. The controller should be placed in a central position on the motherboard, closer to the memory load if possible, but not excessively far from the clock chip or the processor. Insure the VSEN2 connection is properly sized to carry 250mA without significant resistive losses; similar guideline applies to the VCLK output, which can deliver as much as 800mA (typical). As the current for the VCLK output is provided from the ATX 3.3V, the connection from the 3V3 pin to the 3.3V plane should be sized to carry the maximum clock output current while exhibiting negligible voltage losses. Similarly, the current for the 3.3VSB output is provided from the 5VSB pin, and the output current on pin DRV2 from the 5V pin - for best results, insure these pins are connected to their respective sources through adequate traces. The pass transistors should be placed on pads capable of heatsinking matching the device's power dissipation. Where applicable, multiple via connections to a large internal plane can significantly lower localized device temperature rise. Placement of the decoupling and bulk capacitors should follow a placement reflecting their purpose. As such, the high-frequency decoupling capacitors should be placed as close as possible to the load they are decoupling; the ones decoupling the controller close to the controller pins, the ones decoupling the load close to the load connector or the load itself (if embedded). Even though bulk capacitance (aluminum electrolytics or tantalum capacitors) placement is not as critical as the high-frequency capacitor placement, having these capacitors close to the load they serve is preferable. The only critical small signal component is the soft-start capacitor, CSS. Locate this component close to SS pin of the control IC and connect to ground through a via placed close to the capacitor's ground pad. Minimize any leakage current paths from SS node, since the internal current source is only 10A.
ISS - soft-start current (typically 10A) CSS - soft-start capacitor VBG - bandgap voltage (typically 1.26V)
(COUT x VOUT) - sum of the products between the
capacitance and the voltage of an output (total charge delivered to all outputs). Due to the various system timing events, it is recommended that the soft-start interval not be set to exceed 30ms.
Shutdown
In case of a FAULT condition that might endanger the computer system, or at any other time, all the HIP6500 outputs can be shut down by pulling the SS pin below the specified shutdown level (typically 0.8V) with an open drain or open collector device capable of sinking a minimum of 2mA. Pulling the SS pin low effectively shuts down all the pass elements. Upon release of the SS pin, the HIP6500 undergoes a new soft-start cycle and resumes normal operation in accordance to the ATX supply and control pins status.
11
HIP6500
d
+12VIN +5VSB C12V 12V SS CHF1 CSS CBULK1 VOUT1 LOAD Q2 CHF3 VOUT3 3V3DL LOAD CBULK3 DLA 5V 3V3DLSB CBULK5 CHF5 LOAD 3V3SB C5VSB 5VSB 5VDLSB VOUT5 5VDL Q4 CIN
Also, during the transition between active and sleep states, there is a short interval of time during which none of the power pass elements are conducting - during this time the output capacitors have to supply all the output current. The output voltage drop during this brief period of time can be easily approximated with the following formula:
tt V OUT = I OUT x ESR OUT + --------------- , where C OUT
VOUT - output voltage drop
ESROUT - output capacitor bank ESR IOUT - output current during transition
HIP6500
Q5 +5VIN VOUT2 VCLK VSEN2 GND DRV2 Q1 LOAD CHF2
COUT - output capacitor bank capacitance tt - active-to-sleep or sleep-to-active transition time (10s typ.) The output voltage drop is heavily dependent on the ESR (equivalent series resistance) of the output capacitor bank, the choice of capacitors should be such as to maintain the output voltage above the lowest allowable regulation level.
Q3 3V3 CBULK4
CBULK2
VCLK (VOUT4) Output Capacitors Selection
+3.3VIN
CHF4
LOAD
KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT/POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE
The output capacitor for the VCLK linear regulator provides loop stability. Figure 13 outlines a capacitance vs. equivalent series resistance envelope. For stable operation and optimized performance, select a COUT4 capacitor or combination of capacitors with characteristics within the shown envelope.
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FIGURE 12. PRINTED CIRCUIT BOARD ISLANDS
A multi-layer printed circuit board is recommended. Figure 12 shows the connections of most of the components in the converter. Note that the individual capacitors each could represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections through vias placed as close to the component terminal as possible. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Ideally, the power plane should support both the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers to create power islands connecting the filtering components (output capacitors) and the loads. Use the remaining printed circuit layers for small signal wiring.
1.0 ESR () 0.1 0.01 10
100 CAPACITANCE (F)
1000
Component Selection Guidelines
Output Capacitors Selection
The output capacitors for all outputs should be selected to allow the output voltage to meet the dynamic regulation requirements of active state operation (S0, S1). The load transient for the various microprocessor system's components may require high quality capacitors to supply the high slew rate (di/dt) current demands. Thus, it is recommended that the output capacitors be selected for transient load regulation, paying attention to their parasitic components (ESR, ESL).
FIGURE 13. COUT4 OUTPUT CAPACITOR
Input Capacitors Selection
The input capacitors for an HIP6500 application have to have a sufficiently low ESR as to not allow the input voltage to dip excessively when energy is transferred to the output capacitors. If the ATX supply does not meet the specifications, certain imbalances between the ATX's outputs and the HIP6500's regulation levels could have as a result a brisk transfer of energy from the input capacitors to
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HIP6500
the supplied outputs. At the transition between active and sleep states, this phenomena could result in the 5VSB voltage dropping below the POR level (typically 4.1V) and temporarily disabling the HIP6500. The solution to a potential problem such as this is using larger input capacitors with a lower total combined ESR.
Q5
If a P-Channel MOSFET is used to switch the 5VSB output of the ATX supply into the 5VDUAL output during S3 and S5 states (as dictated by EN5VDL status), then, similar to the situation where Q1 is a MOSFET, the selection criteria of this device is also proper voltage budgeting. The maximum rDS(ON), however, has to be achieved with only 4.5V of VGS, so a logic level MOSFET needs to be selected. If a PNP device is chosen to perform this function, it has to have a low saturation voltage while providing the maximum sleep current and have a current gain sufficiently high to be saturated using the minimum drive current (typically 20mA).
Transistor Selection/Considerations
The HIP6500 usually requires one P-Channel (or bipolar PNP), two N-Channel MOSFETs and two bipolar NPN transistors. One important criteria for selection of transistors for all the linear regulators/switching elements is package selection for efficient removal of heat. The power dissipated in a linear regulator/switching element is
P LINEAR = I O x ( V IN - V OUT )
Q3,4
The two N-Channel MOSFETs are used to switch the 3.3V and 5V inputs provided by the ATX supply into the 3.3VDUAL and 5VDUAL outputs, respectively, while in active (S0, S1) state. Similar rDS(ON) criteria apply in these cases as well. Unlike the PMOS, however, these NMOS transistors get the benefit of an increased VGS drive (approximately 8V and 7V, respectively).
Select a package and heatsink that maintains the junction temperature below the rating with the maximum expected ambient temperature.
Q1
The active element on the 2.5V/3.3VMEM output has different requirements for each of the two voltage settings. In 2.5V systems utilizing RDRAM (or voltage-compatible) memory, Q1 has to be a bipolar NPN capable of conducting up to 7.5A and exhibit a current gain (hfe) of minimum 40 at this current and 0.7V VCE; in such systems the 2.5V output is actively regulated while in active state. In 3.3V systems (SDRAM or compatible) Q1 has to be an N-Channel MOSFET; in such systems the MOSFET is switched on during active state (S0, S1). The main criteria for the selection of this transistor is output voltage budgeting. The maximum rDS(ON) allowed at highest junction temperature can be expressed with the following equation:
V INmin - V OUTmin r DS ( ON )max = -------------------------------------------------- , where I OUTmax
Q2
The NPN transistor used as sleep state pass element (Q2) on the 3.3VDUAL output has to have a minimum current gain of 100 at 1.5V VCE and 500mA ICE throughout the in-circuit operating temperature range.
VINmin - minimum input voltage VOUTmin - minimum output voltage allowed IOUTmax - maximum output current The gate bias available for this MOSFET is of the order of 8V.
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HIP6500 HIP6500 Application Circuit
Figure 14 shows an application circuit of an ACPIsanctioned power management system for a microprocessor computer system. The power supply provides the 3.3VSB voltage (VOUT1), the PCI 3.3VDUAL voltage (VOUT3), the RDRAM 2.5VMEM memory voltage (VOUT2), the 2.5VCLK clock voltage (VOUT4), and the 5VDUAL voltage (VOUT5) from +3.3V, +5VSB, and +12VDC ATX supply outputs. For systems employing SDRAM memory, replace R1 with 10k and Q1 with an HUF76113SK8. Q4 can also be a PNP, such as an MMBT2907AL. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN9862. Also see Intersil Corporation's web page (http://www.intersil.com) or Intersil AnswerFAX (321-724-7800) for the latest information.
+5VIN +12VIN +3.3VIN +5VSB C1 1F + C3 1F 12V 3V3 5VSB C4 1F C2 220F
VOUT1 3.3VSB + 3V3SB C5 10F 5V Q2 2SD1802 3V3DLSB C6,7 + 2X150F Q3 1/2 HUF76113DK8 3V3DL VCLK 3.3VDUAL C9 1F + C10 220F VOUT4 2.5VMEM C8 1F VSEN2 DRV2 Q1 2SD1802 VOUT2
VOUT3
U1 HIP6500
FAULT/MSEL
C11 + 150F
2.5VCLK C12 1F
5VDLSB R1 1K
Q4 FDV304P
EN5VDL CONFIGURATION HARDWARE SLP_S3 SLP_S5 EN3VDL S3 S5
DLA Q5 1/2 HUF76113DK8 + C14 150F C15 1F
5VDL
VOUT5 5VDUAL
SS C13 0.1F
GND
SHUTDOWN (FROM OPEN-DRAIN N-MOS)
FIGURE 14. TYPICAL HIP6500 APPLICATION DIAGRAM
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HIP6500 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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